As metal-oxide-semiconductor ("MOS") technology continues to advance and the features of the MOS devices shrink, a scaling down in the vertical dimension of the devices typically occurs. Critical to the success of these devices is a reliable, high-quality gate dielectric with a low defect density ("D.sub.o ") and a high breakdown field strength ("F.sub.bd ") that retains its quality during advanced processing. As the overall size of the semiconductors get ultrathin (e.g., less than 7.5 nm), the quality of the oxide (e.g., SiO.sub.2), even under the best possible external growth conditions, is limited by the natural viscoelastic compressive stress generated in the SiO.sub.2 at temperatures below 1000.degree. C. and by the thermal expansion mismatch between silicon substrate and SiO.sub.2. In present applications, a genuine lowering of the D.sub.o in the range of 0.05 to 0.5 cm.sup.-2 has been achieved. For example, oxide/nitride or oxide/nitride/oxide (ONO) structures can attain such low D.sub.o. The Si.sub.3 N.sub.4 --SiO.sub.2 ("silicon nitride-silicon oxides") interface, however, is invariably associated with a high density of interface states ("Q.sub.it ") that cannot be annealed out easily because the Si.sub.3 N.sub.4 layer is impervious to diffusion of oxidizing species. These multi-layered dielectrics are unsuitable as gate dielectrics in advanced complementary metal-oxide-semiconductor ("CMOS") integrated circuits, because the interface states can cause charge-induced shift in the threshold voltage and can reduce the channel conductance during operation.
To overcome this problem, the concept of stacking thermally grown and chemical-vapor-deposited ("CVD") SiO.sub.2 structures has been proposed in U.S. Pat. No. 4,851,370 ("the '370 patent"), which is incorporated herein by reference for all purposes. Here, the composite stack is synthesized by a 3-step grow-deposit-grow technique wherein the growing steps are conducted at pressures equal to or greater than one atmosphere. The interface between the grown and deposited SiO.sub.2 layers serves the same purpose as the interface in SiO.sub.2 --Si.sub.3 N.sub.4 structures (i.e., it reduces the.sub.o D by misaligning the defects across the interface). Moreover, the interface traps in stacked oxide structures that can be removed easily by an oxidizing anneal, since the top deposited SiO.sub.2 layer, unlike the Si.sub.3 N.sub.4 film, is transparent to oxidizing species (i.e., it transports them by diffusion). This stacking concept can be applied to any composite dielectric structure with similar results as long as the top deposited dielectric layer is transparent to the oxidizing species.
A few major factors contributing to defects in conventional thin-oxide gate dielectrics are growth-induced micropores and intrinsic stress within the oxide layer. The micropores are 1.0 nm to 2.5 nm in diameter, with an average separation of about 10.0 nm. The pores form at energetically favored sites such as heterogeneities created by localized contaminants, ion-damaged areas, dislocation pileups and other defect areas on the silicon-surface resulting from retarded oxidation in these sites. The pores grow outward as oxidation continues to consume silicon around the pore. Thus, a network of micropores usually exists in SiO.sub.2. The micropore network forms potential short-circuit paths for diffusional mass transport and for current leakage.
In addition, the stress within a SiO.sub.2 layer, often accentuated by complex device geometries and processing, usually increases both the size and density of the micropores. Therefore, in developing thin dielectrics with ultra-low D.sub.o, not only should the initial D.sub.o be reduced, but also the local stress-gradients near the Si--SiO.sub.2 interface should be reduced by providing a stress-accommodating layer, such as an interface (between grown and deposited layers) within the dielectric that acts as a stress cushion and defect sink.
The above-mentioned problems become even more acute as the overall size of devices decrease to sub-micron size with ultrathin gate dielectrics (e.g., less than 7.5 nm). Unfortunately, however, the above-discussed conventional stacked-oxide process, which works extremely well in technologies where the semiconductor thickness is greater than 7.5 nm, is not as applicable in technologies having thicknesses less than 7.5 nm. The main reason for this is that in the conventional 3-step stacked process, the SiO.sub.2 is grown in pressures of one atmosphere or greater. In semiconductor technologies where the gate oxide thickness is 10.0 nm or greater, this particular condition is most advantageous because under such atmospheric pressure, the SiO.sub.2 can be grown quite rapidly and one can grow the first grown layer (typically 3.5-7.5 nm) with good uniformity. This rapid growth is highly desirable, f or it cuts down in manufacturing time, and thus, overall production costs. This same rapid growth, which is so advantageous in technologies with gate oxide thickness of 10.0 nm or greater is less desirable in sub-0.5 micron semiconductor technologies because the oxides grow too quickly, which makes thicknesses harder to control. As such, the oxide layers are less uniform in thickness, which is unacceptable.
Accordingly, what is needed in the art is a stacked-oxide process that provides semiconductors having thicknesses of less than 10.0 nm and, more advantageously less than 7.5 nm, and yet provides a semiconductor that has a low defect density ("D.sub.o ") and a high breakdown field strength ("F.sub.bd ") that retains its quality during advanced processing. The present invention addresses this need.